Field of the Invention
The invention is related to the Configurable Non-Volatile Content Addressable Memory (CNVCAM). In particular, the memory of the invention can be configured to store non-volatile content data and searched by input content data. Conventionally, the memory data stored in volatile and non-volatile random access memory are only accessed by address codes with the prior knowledge of their storage locations. Arrays of CNVCAM devices of the invention can be configured to form the basic information processing units similar to a genetically configured neuron layer for processing information in the biological nervous system, where the content of information is extracted from a broadcasting field of information signals and the perceptive information from the neuron layer is generated and propagated into its next connecting neuron layers as the feed-forward signal processing.
Description of the Related Art
In the modern Von-Neumann computing architecture as shown in FIG. 1, the Central Process Unit (CPU) 10 obtains the instructions and data from the main memory units 11 by the address pointers. The CPU 10 includes a main memory 11, an arithmetic and logic unit 12, input/output equipment 13 and a program control unit 14. Prior to the computation process, CPU 10 points to the address codes of the initial instruction and data in the main memory 11 for execution. The digital data are then sequentially processed with clock steps from the arithmetic and logic unit 12 in CPU 10 according to the instructions and data accessed by the address pointer for the main memory 11. The consumed power for completing a computing process is given by P˜f C VDD2, where f is the clock frequency, C is the total circuit capacitance, and VDD is the positive voltage supply for digital circuitry. Accordingly, the energy required for running a computation process sequence is proportional to the numbers of clock steps to complete the whole instructions, the times of accessing the main memory 11, and charging/discharging the total capacitances of the active circuitries. The more instruction steps and memory data accessing times to complete the computation process, the more energy and time are consumed for digital circuitries. For example, a digital content search operation in a memory requires multiple data transmission and comparison steps between the arithmetic and logic unit 12 and the main memory 11. The consumed energy and searching time for searching a content data in a large memory database become very inefficient as the general practice of running programmed software with multiple times of memory data accessing and data comparison in the present Von-Neumann computing system.
In order to improve the search operation efficiency, Content Addressable Memory (CAM) has been applied in computing systems for speedy operations such as internet packet routing or tagging computing instructions and parameters in cache memory. For a typical CAM operation, a digital content is broadcasted into the memory unit with pre-stored multiple memory contents. If the broadcasted digital content is matched with the digital content stored in the memory unit, a matched signal is generated. The whole searching operation is completed within one single clock step. The matched signal can be then further applied for switching on a data channel pathway for the next stage of data processing or initiating an instruction to execute a set of instructions in the computing systems.
SRAM (Static Random Access Memory) are mostly applied for the memory content storage in the conventional CAM cells. FIGS. 2A and 2B show the schematics for a typical 10T (10 Transistors) SRAM-based CAM memory unit cell for the NOR-type match line array and a typical 9T (9 Transistors) SRAM-based CAM unit cell for the NAND-type match line array, respectively. The crossed invertors of the SRAM stores a digital bit “0” with voltage potentials VSS at the node connected to bitline (BL) and VDD at the complementary node connected to the complementary bitline (BL), and a digital bit “1” with the reversed voltage potentials VDD and VSS at the same nodes, respectively. The voltage potentials for the search line (SL) and the complementary search line (SL) are applied with VDD and VSS for a search digital bit “1”, and VSS and VDD for a search digital bit “0”, respectively. For the NOR-type CAM array cell of FIG. 2A, an input digital bit to match the bit stored in the content memory cell, i. e., “1” matching “1” and “0” matching “0”, the transistors M1 and M3 and the transistors M2 and M4 for the matched bit cannot be simultaneously turned, on to conduct the match line (ML) to the ground. For a row of matched NOR-type CAM cells connected to form a single match line (ML), the potential of the match line can never be pulled down to the ground. Any one of not-matched bits for the row of CAM cells will result in connecting the match line to the ground.
For the NAND-type CAM array cell of FIG. 2B, if an input digital bit matches the bit stored in the content cell, either M2 or M3 in the CAM cell is turned on to pass VDD to the gate of M1. The voltage potential, (VDD−Vth), where Vth is threshold voltage of M2 and M3, at the gate of M1 is enough to turn M1 on to connect the left portion of the match line with the right portion of the match line together. The broken match lines connected through multiple M1s of the row between CAM cells form a single conducting match line by turning all M1s “on” for the matched bits in the row of the NAND-type match line CAM array. Any one of not-matched bits will result in an electrically broken match line (ML) for the row.
Although SRAM-based CAM is very efficient in power and speed for memory content search operation in CPU, the cost for SRAM-based CAM has been limiting the applications of large memory arrays due to their large cell sizes (9T for NOR-type and 10T for NAND-type) to occupy much of the silicon areas in Integrated Circuit (IC). The high cost leads to the applications of smaller CAM memory densities in the kilo-byte range for tagging L1 and L2 cache memory in CPU. Therefore a smaller CAM cell size with fewer device components is very desirable for the more high density CAM applications.
In another aspect of CAM applications in computing system, configurable non-volatile CAM cells can provide memory configurability and non-volatility. That is, the configurability and non-volatility of CAM can provide an algorithm for self-adaptively configuring the computing pathways learned from the previous recorded history and storing the non-volatile content and pathway data without the power requirement for keeping the memory data.
To fulfill the objectives, we apply a pair of complementary non-volatile memory devices and one MOSFET (Metal Oxide Semiconductor Field Effect Transistor) to form a basic CAM cell. A digital content bit can be configured in the complementary pair of the non-volatile devices, where each non-volatile memory device of the complementary pair can electrically connect its two device terminals by setting to the “conducting state” and electrically disconnect from its two device terminals by setting to the “non-conducting state”. The non-volatile CAM cells can be configured to form a NOR-type match line array and an NAND-type match line array, respectively. A string of input digital content data (a byte, a word, or a sentence) signals can be simultaneously broadcasted into the configured non-volatile CAM array for a digital content match. The matched signals can be then applied for triggering the sequential data processing, instruction execution, and both.